By Topic

Multiplexed buses: the endian wars continue

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

The issue of data exchange between type-1 and type-2 buses, which multiplex the first data byte (which has the lowest address) with the least and most significant portions of the address, respectively, is considered. In an analogy based on Gulliver's Travels, the associated architectures have been dubbed little-endian and big-endian processors, respectively. It is pointed out that the byte order within integers and the byte order during transmission can differ. Therefore, the big and little adjectives are used to describe the order of bytes within integers, and the acronyms Mad and Sad to describe the order of bytes (most versus least important first) during transmission on a multiplexed address-data bus. After a review of the endian ordering issues, it is concluded that big- and little-endians can use the same bus standard. For high-performance serialized buses, the mad-endian order seems superior to a sad-endian order. For consistency between serialized and multiplexed parallel buses of various widths, the mad-endian order is proposed for future multiplexed standards. To minimize the interface costs to mad-endian buses, a big-endian order is proposed for shared data also.<>

Published in:

Micro, IEEE  (Volume:10 ,  Issue: 3 )