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Register-transfer level deductive fault simulation using decision diagrams

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3 Author(s)
Reinsalu, U. ; Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn, Estonia ; Raik, J. ; Ubar, R.

The paper presents a deductive method for register-transfer level fault simulation on the system model of high-level decision diagrams. The method is based on the bit coverage fault model, which has been proven to have a good correspondence with gate-level structural faults. Experiments on ITC99 benchmark circuits have been carried out showing the feasibility of the proposed approach.

Published in:

Electronics Conference (BEC), 2010 12th Biennial Baltic

Date of Conference:

4-6 Oct. 2010