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In practice, sequential circuits happen to be the most common type of logic circuits. Switching in sequential circuits is the hardest to estimate due to the complex higher order dependencies in the switching profile, induced by the spatio-temporal components of the circuit and mainly caused by the state feedbacks that are present. These state feedbacks do not exist in combinational circuits. In this paper, a new methodology is developed to calculate the value of the average power consumption of sequential CMOS circuits. The methodology is accurate while other methodologies produce approximate results. It is based on the concept of Logic Pictures. To verify the correctness, the methodology was applied to four ISCAS89 benchmark circuits. The obtained results were identical to those produced by Monte Carlo simulations.