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Reducing multithreaded frame cache miss ratio by prefetching and working frame set scheduling

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3 Author(s)
jongpil Choi ; Seoul Nat. Univ., South Korea ; Soonhoi Ha ; Chushik Jhon

In software-oriented multithreading execution model, the compiler identifies the remote accesses and performs fast context switches to hide remote access latency. In TAM model of execution, threads access the local memory through a data structure called “frame”. This paper introduces a cache memory for frame structure and applies two techniques to reduce the cache miss ratio. One is a frame prefetching, which is based on the frame scheduling information, and the other is a changing frame execution sequences by the working frame set concept, multithreading simulation is performed using benchmark programs and causes of cache misses are classified and analyzed. This paper shows the promising result that the frame prefetching based on scheduling information is very effective to reduce the cache miss ratio. But the effect of reordering the sequence of the frame execution is not so big than the prefetching

Published in:

Algorithms & Architectures for Parallel Processing, 1996. ICAPP 96. 1996 IEEE Second International Conference on

Date of Conference:

11-13 Jun 1996