By Topic

An orthogonal multiprocessor for ATM switch system

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Liang-Teh Lee ; Dept. of Comput. Sci. & Eng., Tatung Inst. of Technol., Taipei, Taiwan ; Po-Hsian Huang ; Kuen-Huann Hwang

Asynchronous Transfer Mode (ATM) presents an evolutionary path to provide high bandwidth services and integrates many existing networks into a common architecture. However, ATM should provide native packet services, yet the cell relay method of ATM cannot efficiently fit packet service, especially in heavy traffic. In this paper, we employ an OrthogonaI Multiprocessor (OMP) architecture using Dual-Port memory to enhance the CPU power and eliminate the bus contention problem. The proposed architecture called EOMPA (Enhanced OMP Architecture) also applies a multi-level switch method to fit the multifarious traffics

Published in:

Algorithms & Architectures for Parallel Processing, 1996. ICAPP 96. 1996 IEEE Second International Conference on

Date of Conference:

11-13 Jun 1996