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Design and research of 8-bit Multiplier designed by maximum delay-difference stream-line processing

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3 Author(s)
Feng Youming ; CASET, Beijing, China ; Weimin Li ; Wan Da

An 8-bit Multiplier about the critical technology in parallel manipulating and high-performance processing was designed and manufactured in our laboratory. The suitable logic units and conversion were designed to decrease the disadvantageous effects of CMOS circuits effectively and raise circuit speed. Redundant inverter logic was used to adjust the length of the logic chains. The circuit was disunited into parts according to wafer structure and the characteristic of circuits. The logic simulation and post layout simulation were adapted to adjust the delay of logic chains

Published in:

ASIC, 1996., 2nd International Conference on

Date of Conference:

21-24 Oct 1996