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Low-power consumption architecture for embedded processor

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5 Author(s)
Yoshida, Y. ; IC Dev. Center, Sharp Corp., Nara, Japan ; Bao-Yu Song ; Okuhata, H. ; Onoye, T.
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A low-power processor architecture is described dedicatedly for embedded application programs by means of an object code compression approach. This approach unifies duplicated instructions existing in the embedded program and assigns a simple number to each distinct instruction. An instruction decompressor is constructed in an embedded processor, which is to generate an object code from a compressed object code (pseudo code) input. A single-chip implementation of this decompressor together with a processor core can effectively reduce the bandwidth required for the I/O interface. Experiments are applied to an embedded processor ARMG10 to demonstrate the practicability of the proposed approach

Published in:

ASIC, 1996., 2nd International Conference on

Date of Conference:

21-24 Oct 1996