Modeling and simulation of logic circuits using CNFETs and interconnects

In this paper a new RLC model of a CNFET is presented. The S parameter formulation and analysis is utilized to investigate this two port model for drain to source signal transmission. The characteristic of the new topology is that using CNT interconnects instead of metallic ones, makes the model comfortable to be used in structures with more than one transistor connected to each other like VLSI circuits. Some logic circuits are simulated due to this approach in the end. All simulations are done in software “ADS 2008”.