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Near-threshold full adders for ultra low-power applications

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2 Author(s)
Jianping Hu ; Faculty of Information Science and Technology, Ningbo University, Zhejiang 315211, China ; Xiaoying Yu

Scaling supply voltage is an efficient technique to achieve low energy delay product (EDP). This paper investigates static CMOS, DCVSL, CPL and TG logic full adders in sub-threshold and super-threshold region in terms of low EDP. All circuits are simulated with HSPICE at a PTM 65nm CMOS technology by varying supply voltages from 0.2V to 1.1V with 0.1V steps. The simulation results demonstrate that lowering supply voltage is advantageous, especially in medium-voltage region (700mv-800mv) which yields the best EDP. In addition, it is shown that the optimum supply voltage of the full adders varies slightly with logic style.

Published in:

Circuits,Communications and System (PACCS), 2010 Second Pacific-Asia Conference on  (Volume:1 )

Date of Conference:

1-2 Aug. 2010