By Topic

Near-threshold full adders for ultra low-power applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Jianping Hu ; Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo, China ; Xiaoying Yu

Scaling supply voltage is an efficient technique to achieve low energy delay product (EDP). This paper investigates static CMOS, DCVSL, CPL and TG logic full adders in sub-threshold and super-threshold region in terms of low EDP. All circuits are simulated with HSPICE at a PTM 65nm CMOS technology by varying supply voltages from 0.2V to 1.1V with 0.1V steps. The simulation results demonstrate that lowering supply voltage is advantageous, especially in medium-voltage region (700mv-800mv) which yields the best EDP. In addition, it is shown that the optimum supply voltage of the full adders varies slightly with logic style.

Published in:

Circuits,Communications and System (PACCS), 2010 Second Pacific-Asia Conference on  (Volume:1 )

Date of Conference:

1-2 Aug. 2010