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In this paper, a low-power high-speed fully integrated mixed-signal quadrature demodulator with an embedded multi-gigabit modem in 90 nm CMOS technology is presented. A wide dynamic-range automatic gain control (AGC) is implemented to avoid clipping distortion experienced by the baseband ADCs. By reusing the power detector circuit within the AGC, analog signal processor is introduced to recover OOK modulated signals up to 2.5 Gb/s for an additional power consumption of 7.5 mW. Integrated with ultra-low-power, 3 mW, 3 GS/s, 3-bit ADCs and high-speed digital modem, the system requires neither external synchronization controls nor processing to demodulate BPSK modulated signals up to 3.5 Gb/s and DBPSK modulated signals up to 1.3 Gb/s. The baseband modem incorporates a mixed-signal, timing-recovery loop to sample the symbols at the optimum SNR based on a high-speed Gardner timing-error detector for an additional power consumption of 14 mW. The analog front-end consists of IQ mixers, a 13 GHz QVCO, frequency synthesizers, and a baseband AGC for an overall power consumption of 52 mW. The entire receiver chip occupies an area of 1.275 × 1.19 mm2. To the best of authors' knowledge, this demonstrates the maximum throughput at the minimum power budget and highest level integration among all published wireless multi-gigabit, multi-mode, mixed-signal CMOS receivers.
Microwave Theory and Techniques, IEEE Transactions on (Volume:58 , Issue: 12 )
Date of Publication: Dec. 2010