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Hamming Distance Based 2-D Reordering with Power Efficient Don't Care Bit Filling: Optimizing the test data compression method

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3 Author(s)
Mehta, U.S. ; Inst. of Technol., Nirma Univ., Ahmedabad, India ; Devashrayee, N.M. ; Dasgupta, K.S.

This paper presents a method to compress partially specified test data for a given SoC in Automatic Test Equipment (ATE). A method “Hamming Distance Based 2-Dimensional Reordering with Power Efficient Don't Care Bit Filling” is presented for compression of test data in which two dimensional i.e. row and columnwise test vector reordering and power optimized don't care bit filling method is applied. The advantage of the approach is a good compression with very low test power achieved without adding area overhead. The advantages are shown by experimental results with ISCAS benchmark circuits.

Published in:

System on Chip (SoC), 2010 International Symposium on

Date of Conference:

29-30 Sept. 2010