DLABS: A dual-lane buffer-sharing router architecture for networks on chip

A significant portion of the conventional router's area is dedicated to its buffers at the input/output ports. For regular workloads, however, a large number of buffers are always idle while other buffers are always busy. This observation motivates us to design a new router architecture which allows buffers to be shared by multiple input ports. This architecture keeps buffers busy while working together to forward data, reducing the busy cycle times and pressure on each buffer, resulting in an improvement of the overall network performance. Sharing resources like buffers, however, has the potential of causing deadlock in the network. In this work, we propose a dual-lane architecture that is deadlock-free for our buffer-sharing routers, named DLABS (Dual-Lane Buffer-Sharing) routers. We design three DLABS routers and compare against a conventional wormhole router. Experimental results show the smallest DLABS router occupies an area of only 0.62% of a conventional router, but achieves 108% on the throughput per area (TPA) over regular traffic benchmarks. The largest DLABS router occupies 112% of the circuit area of the conventional router, but achieves 164% on the TPA.