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In this paper, a leakage current limited SRAM bitcell operating in subthreshold/nearthreshold region is demonstrated in IBM 0.13 μm CMOS process. Proposed bitcell exhibits wide hysteresis effect, making the design less vulnerable to process variation. Its hold margin is 30.2% and 18.9% greater than conventional 6T SRAM and referenced SRAM (at 400 mV). At the same times, the SRAM trip point voltage changes according to bitline voltages. Its read margin is 45% and 9% greater than conventional 6T SRAM and referenced SRAM (at 400 mV). Dynamic leakage cut off transistor is utilized to reduce leakage current without inducing dynamic energy penalty. Thus, compared to the referenced 4kb SRAM array, proposed array optimum-energy supply voltage is scaled from 400 mV to 310 mV.