Power Efficiency and Linearity Enhancement Using Optimized Asymmetrical Doherty Power Amplifiers

This paper investigates the virtues of the asymmetrical Doherty power amplifier (PA) for improving the average power efficiency, linearity, and peak envelope power. It commences with an in-depth study of the effects of increasing the size of the peaking amplifier's transistor and its conduction angle on the Doherty PA's RF performance. In particular, the impact of the extended current profile of the peaking amplifier and reduced turn-on effects on the soft-turn characteristic are thoroughly analyzed, and their impacts on the average efficiency and peak power are deduced. Furthermore, the aggravation of the memory effects that accompany the gm3-based nonlinear distortion cancellation is experimentally demonstrated. Two asymmetrical Doherty PAs prototypes are fabricated using 80 W and 150 W laterally diffused metal oxide semiconductor field-effect transistors to individually improve average efficiency and linearity. When driven with a four carrier wideband code division multiple access (4C-WCDMA) signal, the asymmetrical Doherty PA allowed for excellent drain efficiency of approximately 50%, along with high linearity of approximately -50 dBc , using a memory polynomial digital predistorter at an average output power of 50 W. To the best of the authors' knowledge, this achieved efficiency is the highest reported in the literature for a high-power Doherty PA implemented in LDMOS technology.