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FPGA-based 112Gb/s coherent DP-QPSK receiver and multi-stage PMD-PDL emulator for fast evaluation of digital signal processing algorithms

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7 Author(s)
Tanimura, T. ; Fujitsu Labs. Ltd., Kawasaki, Japan ; Aoki, Y. ; Nakashima, H. ; Hoshida, T.
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We developed an FPGA based 112Gb/s coherent DP-QPSK receiver and a multi-stage PMD-PDL emulator that resembles real fibre conditions. Long-term, low penalty signal reception under severe PMD (31.2ps mean) and PDL (1.3dB mean) is experimentally demonstrated.

Published in:

Optical Communication (ECOC), 2010 36th European Conference and Exhibition on

Date of Conference:

19-23 Sept. 2010