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Efficient Variability-Aware NBTI and Hot Carrier Circuit Reliability Analysis

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2 Author(s)
Elie Maricau ; Department of Electrical Engineering, Katholieke Universiteit, Leuven, Belgium ; Georges Gielen

This paper discusses an efficient method to analyze the spatial and temporal reliability of analog and digital circuits. First, a SPICE-based reliability simulator with automatic step-size control is proposed. Both hot carrier degradation and negative bias temperature instability are included in the simulator. Next, a method to analyze the interaction between process variability effects and circuit aging is introduced. This method is based on a screening experimental design (DoE) succeeded by a set of regression DoEs, resulting in a good speed-accuracy tradeoff with a nearly linear complexity for all circuits under test. Finally, based on the DoE analysis, a circuit response surface model (RSM) is derived. The RSM is used for further circuit reliability analysis such as circuit weak spot detection and yield calculation as a function of circuit lifetime. The proposed method is validated over a broad range of both analog and digital circuits. Yield simulation time is reduced with up to three orders of magnitude, when compared to standard Monte Carlo-based techniques and while still maintaining simulation accuracy.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:29 ,  Issue: 12 )