Referenced Items are not available for this document.
The design and measurement of a high-speed optical receiver is presented. The intrisically low speed of a silicon photodiode is increased by a new photodiode structure which combines a high speed and a high responsivity. On top of this, an equalizer is used to increase the attainable bit rate even more. The receiver, existing from a photodiode, TIA, equalizer and post amplifier is integrated in a standard 130 nm CMOS technology. At a bit rate of 5.5 Gbit/s and an optical input power of -3.4 dBm, the BER is below 10-12. The power consumption is only 58.5 mW.
Published in:
ESSCIRC, 2010 Proceedings of the
Date of Conference: 14-16 Sept. 2010
- Page(s):
- 542 - 545
- ISSN :
- 1930-8833
- Print ISBN:
- 978-1-4244-6662-7
- INSPEC Accession Number:
- 11630671
- Conference Location :
- Seville
- Digital Object Identifier :
- 10.1109/ESSCIRC.2010.5619763
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