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A 5.5 Gbit/s optical receiver in 130 nm CMOS with speed-enhanced integrated photodiode

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2 Author(s)
Tavernier, F. ; K.U. Leuven ESAT-MICAS, Heverlee, Belgium ; Steyaert, M.

The design and measurement of a high-speed optical receiver is presented. The intrisically low speed of a silicon photodiode is increased by a new photodiode structure which combines a high speed and a high responsivity. On top of this, an equalizer is used to increase the attainable bit rate even more. The receiver, existing from a photodiode, TIA, equalizer and post amplifier is integrated in a standard 130 nm CMOS technology. At a bit rate of 5.5 Gbit/s and an optical input power of -3.4 dBm, the BER is below 10-12. The power consumption is only 58.5 mW.

Published in:

ESSCIRC, 2010 Proceedings of the

Date of Conference:

14-16 Sept. 2010