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A 100kHz–10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC ΣΔ modulator in 1.2-V 90-nm CMOS

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6 Author(s)
Morgado, A. ; IMSE-CNM, Univ. of Seville, Seville, Spain ; del Rio, R. ; de la Rosa, J.M. ; Bos, L.
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This paper presents an adaptive 1.2-V 90-nm CMOS cascade two-stage (2-2) SC ΣΔ modulator with 3-level quantization and unity signal transfer function in both stages. The chip reconfigures its loop filter order (either 2nd or 4th-order), clock frequency (from 40 to 240 MHz) and scales power according to the required specifications for different wireless standards, covering: GSM, Bluetooth, GPS, UMTS, DVB-H and WiMAX. Measurements feature a dynamic range of 78/70/71.5/66/62/52dB and a peak signal-to-(noise+distortion) ratio of 72.3/68.0/65.4/63.3 /59.1/48.7dB within 100kHz/500kHz/1MHz/2MHz/4MHz/10MHz, while consuming 4.6/5.35/6.2/8/8/11mW, respectively. These results show a competitive performance with the state-of-the-art multi-standard ΣΔ modulators, covering one of the widest regions in the DR-vs.-Bandwidth plane.

Published in:

ESSCIRC, 2010 Proceedings of the

Date of Conference:

14-16 Sept. 2010

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