Referenced Items are not available for this document.
A 12-bit 30-MS/s pipelined ADC is realized using single-stage, low-gain, switched class-AB amplifiers. Nonlinear errors due to finite gain are addressed using a deterministic digital background calibration scheme that employs amplifier duty-cycling to minimize the power overhead. The presented ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near Nyquist. The corresponding figure of merit is 72 fJ/conversion-step.
Published in:
ESSCIRC, 2010 Proceedings of the
Date of Conference: 14-16 Sept. 2010
- Page(s):
- 378 - 381
- ISSN :
- 1930-8833
- Print ISBN:
- 978-1-4244-6662-7
- INSPEC Accession Number:
- 11630692
- Conference Location :
- Seville
- Digital Object Identifier :
- 10.1109/ESSCIRC.2010.5619722
- Product Type:
- Conference Publications
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