By Topic

A 12-bit, 30-MS/s, 2.95-mW pipelined ADC using single-stage class-AB amplifiers and deterministic background calibration

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Justin Kyung-Ryun Kim ; Department of Electrical Engineering, Stanford University, Stanford, CA, USA ; Boris Murmann

A 12-bit 30-MS/s pipelined ADC is realized using single-stage, low-gain, switched class-AB amplifiers. Nonlinear errors due to finite gain are addressed using a deterministic digital background calibration scheme that employs amplifier duty-cycling to minimize the power overhead. The presented ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near Nyquist. The corresponding figure of merit is 72 fJ/conversion-step.

Published in:

ESSCIRC, 2010 Proceedings of the

Date of Conference:

14-16 Sept. 2010