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A 11.1-bit ENOB 50-MS/s pipelined A/D converter in 130-nm CMOS without S/H front end

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2 Author(s)
Jürg Treichler ; Integrated Systems Laboratory, ETH Zurich, 8092 Zurich, Switzerland ; Qiuting Huang

This paper describes the implementation of a 14-bit pipelined analog-to-digital converter (ADC) operating at a sampling frequency of 50MS/s with an effective resolution of 11.1 bit at Nyquist rate, fabricated in a 130-nm technology with a supply voltage of 1.2 volts and a power consumption of less than 110 mW. The ADC consists of differently scaled 1.5-bit pipeline stages only and dispenses with the sample-and-hold (S/H) front-end circuit. While a calibration algorithm measures and digitally compensates for possible capacitor mismatch in the foremost stages, self-calibrating comparators improve the accuracy of the initial stage, and a self-calibrating delay line creates additional clock edges that are delayed with respect to the master clock by a time lag proportional to the sampling period.

Published in:

ESSCIRC, 2010 Proceedings of the

Date of Conference:

14-16 Sept. 2010