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Three-Dimensional Chip Stack With Integrated Decoupling Capacitors and Thru-Si Via Interconnects

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13 Author(s)
Dang, B. ; IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA ; Shapiro, M. ; Andry, P. ; Tsang, C.
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In this letter, the integration of CMOS-compatible thru-Si via (TSV) interconnects with deep-trench decoupling capacitors is demonstrated. Reliability test is performed with a 65-nm CMOS test chip on top of a 3-D Si interposer chip that contains 10 000 TSV interconnects. Multilayer stacking is also demonstrated, and capacitance density of 280 nF/mm2 is achieved with two-layer Si interposer chip stacks.

Published in:

Electron Device Letters, IEEE  (Volume:31 ,  Issue: 12 )

Date of Publication:

Dec. 2010

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