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Optimization of tunnel FETs: Impact of gate oxide thickness, implantation and annealing conditions

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6 Author(s)

We show the impact of process parameters on the electrical performance of complementary Multiple-Gate Tunneling Field Effect Transistors (MuGTFETs), implemented in a MuGFET technology compatible with standard CMOS processing. Firstly, the impact of the gate oxide thickness and implant doping conditions on the tunneling performance is analyzed and compared with TCAD simulations. Secondly, three different annealing conditions are compared: spike anneal, sub-ms laser anneal and low temperature anneal for Solid Phase Epitaxy Regrowth (SPER). Surprisingly, the SPER anneal shows a strong enhanced tunneling current with a record drive current of 46μA/μm at VDD of -1.2V and IOFF of 5pA/μm for Si pTFETs.

Published in:

Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European

Date of Conference:

14-16 Sept. 2010