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Test structure and method for the experimental investigation of internal voltage amplification and surface potential of ferroelectric MOSFETs

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3 Author(s)
Rusu, A. ; Nanolab, Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland ; Salvatore, G.A. ; Ionescu, A.M.

In this paper we report the fabrication and detailed electrical characterization of a novel test structure based on Metal-Ferroelectric-Oxide-Semiconductor transistor with internal metal contact, aiming at extracting the surface potential and the investigation of internal voltage amplification expected due to negative capacitance effect. The proposed test structure is p-Fe-FET with a thin Al contact in-between the PVDF ferroelectric and a pedestal oxide, enabling access to the internal voltage potential in all the regimes of operations, from weak to strong inversion. Moreover, the capacitances of reference MOS transistor and of Fe-FET can be independently probed. The test structure was fabricated on low doped silicon with STI isolation, in n-implanted well, with a gate stack including 6.5 nm of SiO2, 50 nm of Al, 100 nm of P(VDF-TrFE) and Au as top contact. The fabricated p-type Fe-FET has an excellent subthreshold slope of 75 mV/decade, Ion/Ioff > 107 and Ioff in the pA range. Based on voltage and capacitive measurements, the Fe-FET surface potential is extracted for the first time. We demonstrate that the internal node voltage amplitude can be controlled by the sweeping conditions of the polarization loops. The test structure appears highly suited for the future investigation of the negative capacitances and of more complex ferroelectric gate stacks.

Published in:

Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European

Date of Conference:

14-16 Sept. 2010