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A 32nm 0.5V-supply dual-read 6T SRAM

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15 Author(s)
Kuang, J.B. ; Austin Res. Lab., IBM Corp., Austin, TX, USA ; Schaub, J.D. ; Gebara, F.H. ; Wendel, D.
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Dual read port SRAMs play a critical role in high performance cache designs, but stability and sensing challenges typically limit the low voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cycle access latency, in a 32nm metal-gate partially depleted (PD) SOI technology, for low-voltage applications. Hardware exhibits robust operation at 348MHz and 0.5V with a read and write power of 3.33 and 1.97mW, respectively, per 4.5KB active array with both read ports accessed at the highest activity data pattern. At a 0.6V supply, an access speed of 1.2GHz is observed.

Published in:

Custom Integrated Circuits Conference (CICC), 2010 IEEE

Date of Conference:

19-22 Sept. 2010