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Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding

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3 Author(s)
Mitsumasa Koyanagi ; New Industry Creation Hatchery Center (NICHe), Tohoku University, Sendai, Japan 980-8579 ; Takafumi Fukushima ; Tetsu Tanaka

Three-dimensional (3-D) integration technologies using through-silicon vias (TSV's) are described. We have developed a 3-D integration technology using TSV's based on a wafer-to-wafer bonding method for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have developed a new 3-D integration technology based on a reconfigured wafer-to-wafer bonding method called a super-chip integration. A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip integration.

Published in:

Custom Integrated Circuits Conference (CICC), 2010 IEEE

Date of Conference:

19-22 Sept. 2010