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Statistical modeling and post manufacturing configuration for scaled analog CMOS

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3 Author(s)
Gokce Keskin ; Carnegie Mellon University, Dept. of ECE, 5000 Forbes Ave., Pittsburgh, 15213, USA ; Jonathan Proesel ; Larry Pileggi

Process variations in advanced CMOS process nodes limit the benefits of scaling for analog designs. In the presence of increasing random intra-die variations, mismatch becomes a significant design challenge in circuits such as comparators. In this paper we describe and demonstrate the details of a statistical element selection (SES) methodology that relies on choosing a subset of selectable circuit elements (e.g., input transistors in a comparator) to achieve the desired specification (e.g., offset). Silicon results from a 65nm test chip demonstrate that SES can achieve an order of magnitude better matching than both redundancy and Pelgrom-model sizing given the same core circuit area.

Published in:

Custom Integrated Circuits Conference (CICC), 2010 IEEE

Date of Conference:

19-22 Sept. 2010