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Analyzing the impact of Double Patterning Lithography on SRAM variability in 45nm CMOS

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5 Author(s)
Joshi, V. ; Univ. of Michigan, Ann Arbor, MI, USA ; Wieckowski, M. ; Chen, G.K. ; Blaauw, D.
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This paper analyzes the impact of Double Patterning Lithography (DPL) on 6T SRAM variability. A test chip is implemented in a 45nm CMOS process that uses DPL. Measurements from 75 dies demonstrate a significant impact of DPL on SRAM failures. Extensive analysis demonstrates that DPL induced mismatch considerably increases functional failures in SRAM cells, and degrades yield. We also propose a DPL-aware sizing technique to mitigate yield losses.

Published in:

Custom Integrated Circuits Conference (CICC), 2010 IEEE

Date of Conference:

19-22 Sept. 2010