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Varactors can be used to control delays and limit ISI-related signal integrity degradation for on-chip global interconnect. This paper presents a varactor-based “near-speed-of-light” interconnect design. In this design, the varactors compensate for delay variations enabling a simple, source-synchronous solution for clock-and-data recovery. Furthermore, the varactors provide pulse shaping that reduces ISI. We implemented these interconnects in the TSMC 90 nm CMOS process and present test results for 16 mm long lines.