Referenced Items are not available for this document.
We describe the design and analysis of 3D-MAPS, a 64-core 3D-stacked memory-on-processor running at 277 MHz with 63 GB/s memory bandwidth, sent for fabrication using Tezzaron's 3D stacking technology. We also describe the design flow used to implement it using industrial 2D tools and custom add-ons to handle 3D specifics.
Published in:
Custom Integrated Circuits Conference (CICC), 2010 IEEE
Date of Conference: 19-22 Sept. 2010
- Page(s):
- 1 - 4
- ISSN :
- 0886-5930
- Print ISBN:
- 978-1-4244-5758-8
- INSPEC Accession Number:
- 11627850
- Conference Location :
- San Jose, CA
- Digital Object Identifier :
- 10.1109/CICC.2010.5617464
- Product Type:
- Conference Publications
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