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A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS

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6 Author(s)
Takemoto, T. ; Central Res. Lab., Hitachi, Ltd., Kokubunji, Japan ; Yuki, F. ; Yamashita, H. ; Tsuji, S.
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A 25 Gb/s × 4-channel transimpedance amplifier has been realized in 65-nm CMOS technology. It achieves transimpedance gain of 69.8 dBΩ, bandwidth of 22.8 GHz, and gains flatness of under ±2 dB after equalizing the effect of transmission loss, incorporating gain-stage amplifier with flat frequency response, and 50Ω-output driver with an analogue equalizer. The proposed TIA dissipates only 74 mW/ch and demonstrates the transimpedance bandwidth products per DC power of 952.1 GHzΩ/mW and crosstalk of less than -17 dB. The sensitivity at bit error rate (BER) of less than 10-12 was measured to be the optical input power of -7.4 dBm for multi-channel operation at the data rate of 25 Gb/s, and also demonstrates only 0.8 dB power penalty.

Published in:

Custom Integrated Circuits Conference (CICC), 2010 IEEE

Date of Conference:

19-22 Sept. 2010

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