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Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS

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5 Author(s)
Tao Jiang ; Oregon State University, Corvallis, 97331, USA ; Wing Liu ; Freeman Y. Zhong ; Charlie Zhong
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A single channel, loop-unrolled, asynchronous successive approximation (SAR) ADC fabricated in 40nm CMOS is presented. Compared with a conventional SAR structure that exhibits significant delay in the digital feedback logic, the proposed 6b SAR-ADC employs a different comparator for each bit of conversion, with an asynchronous ripple clock generated after each quantization. With the sample rate limited only by the six delays of the C-DAC settling and comparator quantizations, the 40nm-CMOS SAR-ADC achieves a peak SNDR of 32.9dB and 30.5dB at 1GS/s and 1.25GS/s, respectively, consuming 5.28mW and 6.08mW in a core area less than 170um × 85um.

Published in:

Custom Integrated Circuits Conference (CICC), 2010 IEEE

Date of Conference:

19-22 Sept. 2010