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Reconfigurable mobile stream processor for ray tracing

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3 Author(s)
Hong-Yun Kim ; Dept. of EECS, Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea ; Young-Jun Kim ; Lee-Sup Kim

This paper presents a reconfigurable mobile stream processor for ray tracing. The processor is implemented with 16mm2 area in 0.13μm CMOS technology. The processor adopts a single instruction, multiple thread (SIMT) architecture in order to exploits instruction-level and thread-level parallelism. The SIMT architecture consists of 12 stream processors (SPs). A low hardware utilization caused by a branch divergence in SIMT architecture is addressed by reconfiguring the SPs between scalar SIMT and vector SIMT with negligible hardware overheads. A slim special function unit (SFU) with a table loader reduces the SFU area and look-up table access counts. Reusing previous result for a ray generator reduces its operations by up to 71.9%. The proposed processor achieves a peak performance of 673K rays per second while consuming 156mW.

Published in:

Custom Integrated Circuits Conference (CICC), 2010 IEEE

Date of Conference:

19-22 Sept. 2010