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A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS

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10 Author(s)
Hsieh-Hung Hsieh ; Design Technol. Div., Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan ; Fu-Lung Hsueh ; Chewn-Pu Jou ; Kuo, F.
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In this paper, a novel circuit topology of CMOS divide-by-three injection-locked frequency divider is demonstrated. By using a differential direct injection pair with a LC-tank oscillator, the proposed circuit can perform the division ratio of three while the wide locking range is obtained. Based on the presented circuit architecture, a V-band frequency divider is implemented in 65-nm CMOS for demonstration. Operated at a supply voltage of 1.0 V, the divider core consumes a dc power of 5.2 mW. At an incident power of 0 dBm, the fabricated circuit exhibits an input locking range from 58.6 to 67.2 GHz. The measured output power and locked phase noise at a 1-MHz offset are -10 dBm and -127 dBc/Hz, respectively. To the authors' best knowledge, this work is the first CMOS V-band divide-by-three injection-locked frequency divider owning a locking range over 10% without any tuning mechanism reported to date.

Published in:

Custom Integrated Circuits Conference (CICC), 2010 IEEE

Date of Conference:

19-22 Sept. 2010

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