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Creation of Partial FPGA Configurations at Run-Time

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2 Author(s)
Silva, M.L. ; DEEC, Univ. do Porto, Porto, Portugal ; Ferreira, J.C.

This paper describes and evaluates a method to generate partial FPGA configurations at run-time. The proposed technique is aimed at adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. The approach is based on the availability of a library of partial bit streams for a set of basic components. New partial configurations for circuits defined by net lists of basic components are created by merging together a default bit stream of the target area, the relocated configurations of the components, and the configurations of the switch matrices used for building the connections between the components. An implementation targeting the Virtex-II Pro platform FPGA is described. It runs on the embedded 300 MHz Power PC CPU present in the FPGA. The proof-of-concept implementation was used to create partial configurations at run-time for 20 circuits with up to 21 components and 288 connections. The complete configuration creation process took between 7 s and 97 s.

Published in:

Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference on

Date of Conference:

1-3 Sept. 2010