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Logic simulation is a critical component of the design tool flow in modern hardware development efforts. In this paper a new algorithm for parallel logic simulation is proposed based on a new model of Structurally Synthesized Multiple Input BDDs (SSMIBDD). The SSMIBDDs allow further model size reduction and therefore higher speed of logic simulation than its predecessor SSBDD model. The paper presents a method of SSMIBDD synthesis from the given gate network and the main principles of parallel logic simulation with SSMIBDDs. Experimental data demonstrate in average 2.9 times improvement in the speed of logic simulation because of the reduced number of nodes in SSMIBDDs. Similarly to the SSBDDs, the new model preserves structural information about the circuit, which is needed for processing of faults. The reduced complexity of SSMIBDDs leads to the more powerful fault collapsing and as the result to more efficient fault simulation and fault injection to evaluate the dependability of fault tolerant circuits.
Date of Conference: 1-3 Sept. 2010