A 3 bit 20 GS/s flash ADC in 65 nm low power CMOS technology

A 20 GS/s 3 bit flash ADC with a wide analog bandwidth is realized in a 65 nm CMOS technology. By employing a fourfold parallelization a high sampling rate is achieved, while a large input bandwidth is maintained. The measured effective resolution is between 2 bit and 2.5 bit at a sampling rate of 12.8 GS/s and between 2 bit and 2.3 bit at a sampling rate of 18 GS/s. The power consumption of the ADC core is 2 W, the core area is 0.16 mm².