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In this work, the graded channel concept has been introduced into a fully-depleted 0.15 μm SOI CMOS technology through a commercial industrial fabrication process in order to improve the RF noise performance of deep submicron scale devices. The benefits of using a graded channel transistor are explicit. An improved minimum noise figure is achieved while relaxing the minimum feature size to, at least, one technology node backward. The standard CMOS process is slightly changed by introducing one extra mask only to the fabrication process.