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A digital PLL (DPLL) with a time-to-digital converter (TDC) embedded within a digitally controlled oscillator (DCO) has been implemented in 65 nm CMOS occupying an active area of 0.027 mm . The quantization step of the TDC naturally tracks the DCO period over corners, and therefore requires no calibration. By utilizing an interpolation flip flop, the timing resolution provided by DCO is further enhanced. The DPLL achieves fractional-N operation without a multi-modulus feedback divider, thereby avoiding its complexity and quantization noise. To improve the TDC linearity, a mismatch filtering technique that incorporates cross-coupled resistor network is proposed to achieve a DNL less than 0.04 LSB of the TDC quantization level. The prototype consumes 3.2 mW with an operation frequency ranging from 600 to 800 MHz. The measured DPLL output phase noise at 800 MHz frequency (after a divide-by-two) achieves and dBc/Hz at 1 kHz and 1 MHz offset, respectively.