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Low damage fully self-aligned replacement gate process for fabricating deep sub-100 nm gate length GaAs metal-oxide-semiconductor field-effect transistors

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8 Author(s)
Li, X. ; Nanoelectronics Research Centre, University of Glasgow, Glasgow, G12 8LT, United Kingdom ; Bentley, S. ; McLelland, H. ; Holland, M.C.
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This article describes a process flow which has enabled the first demonstration of functional, fully self-aligned, 40 nm gate length replacement gate enhancement mode GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) with GaxGdyOz as high-κ dielectric, Pt/Au metal gate stack, and SiN sidewall spacers. The flow uses blanket metal and dielectric deposition and low damage dry etch modules. As a consequence, no critical dimension lift-off processes are required. As a gate replacement approach has been developed, the process is suitable for easily incorporating different gate metals, opening the way to work function engineering to control threshold voltage and so is a significant step forward to the demonstration of high performance “siliconlike” III-V MOSFETs.

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Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures  (Volume:28 ,  Issue: 6 )