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A 1.0–4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control

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5 Author(s)
Heesoo Song ; Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea ; Deok-Soo Kim ; Do-Hwan Oh ; Suhwan Kim
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This paper describes the design and implementation of an all-digital clock and data recovery circuit (ADCDR) for multigigabit/s operation. The proposed digitally-controlled oscillator (DCO) incorporating a supply-controlled ring oscillator with a digitally-controlled resistor (DCR) generates wide-frequency-range multiphase clocks with fine resolution. With an adaptive proportional gain controller (APGC) which continuously adjusts a proportional gain, the proposed ADCDR recovers data with a low-jitter clock and tracks large input jitter rapidly, resulting in enhanced jitter performance. A digital frequency-acquisition loop with a proportional control greatly reduces acquisition time. Fabricated in a 0.13-μm CMOS process with a 1.2-V supply, the ADCDR occupies 0.074 mm2 and operates from 1.0 Gb/s to 4.0 Gb/s with a bit error rate of less than 10-14. At a 3.0-Gb/s 231 - 1 PRBS, the measured jitter in the recovered clock is 3.59 psrms and 29.4 pspp, and the power consumption is 11.4 mW.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:46 ,  Issue: 2 )

Date of Publication:

Feb. 2011

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