Referenced Items are not available for this document.
In order to follow the development of image interpretation and data-processing system in photoelectric measurement equipments, a kind of hardware acceleration system is designed where MIMD distributed multi-processor architecture is used with SOPC technology. System hardware is composed of FPGA, SDRAM, SRAM, FLASH, and PCI bridge chip. Four Nios II embedded processors are integrated in a single FPGA chip, and communicate with each other by sharing memory. Experimental results indicate that the system meets the requirements of data-processing system in photoelectric measurement equipments and possesses practical significance for engineering applications.
Published in:
Computer, Mechatronics, Control and Electronic Engineering (CMCE), 2010 International Conference on
(Volume:5
)
Date of Conference: 24-26 Aug. 2010
- Page(s):
- 130 - 132
- Print ISBN:
- 978-1-4244-7957-3
- INSPEC Accession Number:
- 11599093
- Conference Location :
- Changchun
- Digital Object Identifier :
- 10.1109/CMCE.2010.5610019
- Product Type:
- Conference Publications
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