Skip to Main Content
In order to follow the development of image interpretation and data-processing system in photoelectric measurement equipments, a kind of hardware acceleration system is designed where MIMD distributed multi-processor architecture is used with SOPC technology. System hardware is composed of FPGA, SDRAM, SRAM, FLASH, and PCI bridge chip. Four Nios II embedded processors are integrated in a single FPGA chip, and communicate with each other by sharing memory. Experimental results indicate that the system meets the requirements of data-processing system in photoelectric measurement equipments and possesses practical significance for engineering applications.
Computer, Mechatronics, Control and Electronic Engineering (CMCE), 2010 International Conference on (Volume:5 )
Date of Conference: 24-26 Aug. 2010