The implementation of high-speed FFT processor based on FPGA

A method of implementing 256-point, high-speed and 16-bit complex FFT is presented on the radix-4 FFT algorithm. By using a fixed geometry addressing, pipeline designing and block floating point structure, the data has the greater precision and dynamic range. The results show that the design is efficient, strongly extensive and occupies less resource. It is a good method to meet the high-speed digital signal processing requirements.