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Mismatch compensation in current mirrors with FGMOS transistor

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2 Author(s)
Jesús de la Cruz Alejo ; División de Maestría en Ingeniería Mecatrónica, TESE, México, México ; L. Noe Oliva Moreno

This paper presents a technique to solve mismatch compensation problems in current mirrors using the floating gate MOS transistor. To reduce mismatches, the tunneling and injection processes are applied in a 1.2 μm CMOS process. It takes into account the long-term voltage storage as charge on the floating gate of a transistor pMOS. Experimental results justifying these processes are also including. The output current of the current mirror present successful results according to theorical analysis and achieving the mismatch compensation.

Published in:

Electrical Engineering Computing Science and Automatic Control (CCE), 2010 7th International Conference on

Date of Conference:

8-10 Sept. 2010