By Topic

A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Yi-Da Wu ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Chang-Ming Lai ; Lee, Chao-Cheng ; Po-Chiun Huang

This paper presents a technique to reduce the quantization error in fractional division for a wideband fractional-N frequency synthesizer. By using a direct digital synthesis phase accumulator as the fractional divider and a DAC as the phase-to-pulse converter, the quantization error can be much smaller than the one by conventional sigma-delta modulated multi-modulus divider. With small quantization error, a dedicated compensation mechanism is no longer necessary for wide loop bandwidth applications. To demonstrate this concept, a prototype chip was implemented with 0.18-μm CMOS. The synthesizer consumes 19 mA from a 1.8 V supply. With 1 MHz closed-loop bandwidth, the in-band noise is -98 dBc/Hz and the 3 MHz offset noise is -122 dBc/Hz for a 1.8 GHz output. The output exhibited 27 dB phase noise reduction compared to the generic sigma-delta structure. The settling time is 2 μs under a 35 MHz frequency step.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:45 ,  Issue: 11 )