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Dynamic voltage and frequency scaling (DVFS) is an effective way for system-level power saving. However, lowering the supply voltage may cause some concerns including yield loss and speed degradation. This paper presents a fully integrated linear regulator that can dynamically assign the supply voltage of a SRAM cell to improve the read and write margins in a DVFS system. To minimize the timing overhead during mode transitions, this design adopts two separate feedback loops for reference tracking and load regulation. Individual loop optimization makes a fast transient response possible. To verify this concept, a prototype regulator without an external component was designed with a 1.8-V 0.18-μm CMOS. The output voltage could be freely set between 0.9-1.7 V. With a 0.1-V step, the measured rising and falling time was within 10 and 35 ns, respectively. The maximum current efficiency was 94.7% under a 20-mA current loading.