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An ultra-low power CMOS PTAT current source

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3 Author(s)
Carlos Christoffersen ; Department of Electrical Engineering, Lakehead University, Thunder Bay, ON P7B 5E1, Canada ; Greg Toombs ; Ali Manzak

A low-voltage, ultra-low-power sub-threshold proportional to absolute temperature (PTAT) current source is proposed. The new topology generates the PTAT current from the ratio between the drain currents of two transistors in subthreshold operation. Linearity is analyzed and a compensation strategy to improve it is developed. This is the first time such a design scheme is presented. Total current drain for the circuit is approximately 3.8 μA with a minimum supply voltage of 1 V and a PSRR greater than 50 dB at room temperature. The linear range is at least from -40°C to 125°C. The performance of the proposed reference is compared with several existing designs.

Published in:

Argentine School of Micro-Nanoelectronics Technology and Applications (EAMTA), 2010

Date of Conference:

1-9 Oct. 2010