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Efficient coordination of parallel threads of H.264/AVC decoder for performance improvement

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3 Author(s)
Song Hyun Jo ; Dept. of Electron. & Comput. Eng., Hanyang Univ., Seoul, South Korea ; Seongmin Jo ; Yong Ho Song

The H.264/AVC decoder is a video codec standard that provides a high compression rate for a video. This decoder includes various algorithms to enhance the compression effect and consequently requires significant computational capability from processors to execute those algorithms. Since multi-core platforms are being widely used, research has been performed to improve the performance of the software H.264/AVC decoder by parallelizing it within multi-core platforms. However, there are many obstacles to parallelizing the existing decoder due to restrictions such as sequential execution, data subordination, and other limitations of the decoder. The parallelization of the decoder is often limited only to a subset of decoder functions. This paper analyzes such restrictions as the sequential execution and data subordination existent inside the H.264/AVC decoder and suggests a method for controlling the parallel execution of threads in order to bypass such restrictions. The experimental results show that the H.264/AVC decoder proposed parallelization technique achieves a 25% increase in speed compared with that of the existing parallelization approach.

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:56 ,  Issue: 3 )