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An FPGA implementation of chaotic and edge enhanced error diffusion

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2 Author(s)
Chung-Yen Su ; Department of Applied Electronics Technology, NTNU ; You-Lin Sie

Digital halftoning plays a central role in getting more observable grey-levels for either the innovative electronic paper or other less level devices. The hardware implementation of digital halftoning is, however, seldom fully explored. In this paper, we propose a novel implementation of digital halftoning by means of error diffusion. The proposed scheme not only can perform a new method called chaotic and edge enhanced error diffusion, but also can be reduced to perform the conventional Floyd-Steinberg error diffusion. Best of all, our new scheme can produce halftone images with lower worm-like artifacts and sharper image edges. This scheme is mainly composed of four components: gradient-based edge detection, chaotic threshold generation, edge enhanced quantization, and error diffusion. Each circuit design of the four components is illustrated for the first time. Besides, we demonstrate the hardware performance of our scheme by using a field programmable gate array (FPGA) chip to offer possibly further applications.

Published in:

IEEE Transactions on Consumer Electronics  (Volume:56 ,  Issue: 3 )